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80c51 family derivatives 8XC552/562 overview 1996 aug 06 integrated circuits
philips semiconductors 80c51 family derivatives 8XC552/562 overview 2 1996 aug 06 8XC552 overview the 8XC552 is a stand-alone high-performance microcontroller designed for use in real-time applications such as instrumentation, industrial control, and automotive control applications such as engine management and transmission control. the device provides, in addition to the 80c51 standard functions, a number of dedicated hardware functions for these applications. the 8XC552 single-chip 8-bit microcontroller is manufactured in an advanced cmos process and is a derivative of the 80c51 microcontroller family. the 8XC552 uses the powerful instruction set of the 80c51. additional special function registers are incorporated to control the on-chip peripherals. three versions of the derivative exist although the generic term a8XC552o is used to refer to family members: 83c552: 8k bytes mask-programmable rom, 256 bytes ram 87c552: 8k bytes eprom, 256 bytes ram 80c552: romless version of the 83c552 the 8XC552 contains a nonvolatile 8k 8 read-only program memory, a volatile 256 8 read/write data memory, five 8-bit i/o ports and one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80c51), an additional 16-bit timer coupled to capture and compare latches, a fifteen-source, two-priority-level, nested interrupt structure, an 8-input adc, a dual dac pulse width modulated interface, two serial interfaces (uart and i 2 c bus), a awatchdogo timer, and on-chip oscillator and timing circuits. for systems that require extra capability, the 8XC552 can be expanded using standard ttl compatible memories and logic the 8XC552 has two software selectable modes of reduced activity for further power reductioneidle and power-down. the idle mode freezes the cpu and resets timer t2 and the adc and pwm circuitry but allows the other timers, ram, serial ports, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to become inoperative. 83c562 overview the 83c562 has been derived from the 8XC552 with the following changes: ? the sio1 (i 2 c) interface has been omitted. ? the output of port lines p1.6 and p1.7 have a standard configuration instead of open drain. ? the resolution of the a/d converter is decreased from 10 bits to 8 bits. ? the time of an a/d conversion has decreased from 50 machine cycles to 24 machine cycles. all other functions, pinning and packaging are unchanged. this chapter of the users' guide can be used for the 83c562 by omitting or changing the following: ? disregard the description of sio1 (i 2 c). ? the sfrs for the interface: s1adr, s1dat, s1sta, and s1con are not implemented. the two sio1 related flags es1 in sfr ien0 and ps1 in sfr ip0 are also not implemented. these two flag locations are undefined after reset. the interrupt vector for sio1 is not used. ? port lines p1.6 and p1.7 are not open drain but have the same standard configuration and electrical characteristics as p1.0-p1.5. port lines p1.6 and p1.7 have alternative functions. ? the a/d converter has a resolution of 8 bits instead of 10 bits and consequently the two high-order bits 6 and 7 of sfr adcon are not implemented. these two locations are undefined after reset. the 8-bit result of an a/d conversion is present in sfr adch. the result can always be calculated from the formula: 256 v in av ref av ref av ref the a/d conversion time is 24 machine cycles instead of 50 machine cycles, and the sampling time is 6 machine cycles instead of 8 machine cycles. the conversion time takes 3 machine cycles per bit. ? the serial i/o function sio0 and its sfrs s0buf and s0con are renamed to sio, sbuf, and scon. the interrupt related flags es0 and ps0 are renamed es and ps. interrupt source s0 is renamed s. the serial i/o function remains the same. differences from the 80c51 program memory the 8XC552 contains 8k bytes of on-chip program memory which can be extended to 64k bytes with external memories (see figure 1). when the ea pin is held high, the 8XC552 fetches instructions from internal rom unless the address exceeds 1fffh. locations 2000h to ffffh are fetched from external program memory. when the ea pin is held low, all instruction fetches are from external memory. rom locations 0003h to 0073h are used by interrupt service routines. data memory the internal data memory is divided into 3 sections: the lower 128 bytes of ram, the upper 128 bytes of ram, and the 128-byte special function register areas. the lower 128 bytes of ram are directly and indirectly addressable. while ram locations 128 to 255 and the special function register area share the same address space, they are accessed through different addressing modes. ram locations 128 to 255 are only indirectly addressable, and the special function registers are only directly addressable. all other aspects of the internal ram are identical to the 8051. the stack may be located anywhere in the internal ram by loading the 8-bit stack pointer. stack depth is 256 bytes maximum. special function registers the special function registers (directly addressable only) contain all of the 8XC552 registers except the program counter and the four register banks. most of the 56 special function registers are used to control the on-chip peripheral hardware. other registers include arithmetic registers (acc, b, psw), stack pointer (sp), and data pointer registers (dhp, dpl). sixteen of the sfrs contain 128 directly addressable bit locations. table 1 lists the 8XC552's special function registers. the standard 80c51 sfrs are present and function identically in the 8XC552 except where noted in the following sections.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 3 external (ffffh) 64k (2000h) 8192 (1fffh) 8191 (0000h) 0 internal (ea = 1) external (ea = 0) program memory (ffffh) 64k (0000h) 0 external data memory (ffh) 255 (00h) 0 internal data ram special function registers (7fh) 127 internal data memory su00754 overlapped space figure 1. memory map timer t2 timer t2 is a 16-bit timer consisting of two registers tmh2 (high byte) and tml2 (low byte). the 16-bit timer/counter can be switched off or clocked via a prescaler from one of two sources: f osc /12 or an external signal. when timer t2 is configured as a counter, the prescaler is clocked by an external signal on t2 (p1.4). a rising edge on t2 increments the prescaler, and the maximum repetition rate is one count per machine cycle (1mhz with a 12mhz oscillator). the maximum repetition rate for timer t2 is twice the maximum repetition rate for timer 0 and timer 1. t2 (p1.4) is sampled at s2p1 and again at s5p1 (i.e., twice per machine cycle). a rising edge is detected when t2 is low during one sample and high during the next sample. to ensure that a rising edge is detected, the input signal must be low for at least 1/2 cycle and then high for at least 1/2 cycle. if a rising edge is detected before the end of s2p1, the timer will be incremented during the following cycle; otherwise it will be incremented one cycle later. the prescaler has a programmable division factor of 1, 2, 4, or 8 and is cleared if its division factor or input source is changed, or if the timer/counter is reset. timer t2 may be read aon the flyo but possesses no extra read latches, and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while timer t2 is being read. timer t2 is not loadable and is reset by the rst signal or by a rising edge on the input signal rt2, if enabled. rt2 is enabled by setting bit t2er (tm2con.5). when the least significant byte of the timer overflows or when a 16-bit overflow occurs, an interrupt request may be generated. either or both of these overflows can be programmed to request an interrupt. in both cases, the interrupt vector will be the same. when the lower byte (tml2) overflows, flag t2b0 (tm2con) is set and flag t20v (tm2ir) is set when tmh2 overflows. these flags are set one cycle after an overflow occurs. note that when t20v is set, t2b0 will also be set. to enable the byte overflow interrupt, bits et2 (ien1.7, enable overflow interrupt, see figure 2) and t2is0 (tm2con.6, byte overflow interrupt select) must be set. bit twb0 (tm2con.4) is the timer t2 byte overflow flag. to enable the 16-bit overflow interrupt, bits et2 (ie1.7, enable overflow interrupt) and t2is1 (tm2con.7, 16-bit overflow interrupt select) must be set. bit t2ov (tm2ir.7) is the timer t2 16-bit overflow flag. all interrupt flags must be reset by software. to enable both byte and 16-bit overflow, t2is0 and t2is1 must be set and two interrupt service routines are required. a test on the overflow flags indicates which routine must be executed. for each routine, only the corresponding overflow flag must be cleared. timer t2 may be reset by a rising edge on rt2 (p1.5) if the timer t2 external reset enable bit (t2er) in t2con is set. this reset also clears the prescaler. in the idle mode, the timer/counter and prescaler are reset and halted. timer t2 is controlled by the tm2con special function register (see figure 3).
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 4 table 1. 8XC552 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h adch# a/d converter high c6h xxxxxxxxb adcon# adc control c5h adc.1 adc.0 adex adci adcs aadr2 aadr1 aadr0 xx000000b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ctcon# capture control ebh ctn3 ctp3 ctn2 ctp2 ctn1 ctp1 ctn0 ctp0 00h cth3# capture high 3 cfh xxxxxxxxb cth2# capture high 2 ceh xxxxxxxxb cth1# capture high 1 cdh xxxxxxxxb cth0# capture high 0 cch xxxxxxxxb cmh2# compare high 2 cbh 00h cmh1# compare high 1 cah 00h cmh0# compare high 0 c9h 00h ctl3# capture low 3 afh xxxxxxxxb ctl2# capture low 2 aeh xxxxxxxxb ctl1# capture low 1 adh xxxxxxxxb ctl0# capture low 0 ach xxxxxxxxb cml2# compare low 2 abh 00h cml1# compare low 1 aah 00h cml0# compare low 0 a9h 00h dptr: dph dpl data pointer (2 bytes) data pointer high data pointer low 83h 82h 00h 00h af ae ad ac ab aa a9 a8 ien0*# interrupt enable 0 a8h ea ead es1 es0 et1 ex1 et0 ex0 00h ef ee ed ec eb ea e9 e8 ien1*# interrupt enable 1 e8h et2 ecm2 ecm1 ecm0 ect3 ect2 ect1 ect0 00h bf be bd bc bb ba b9 b8 ip0*# interrupt priority 0 b8h pad ps1 ps0 pt1 px1 pt0 px0 x0000000b ff fe fd fc fb fa f9 f8 ip1*# interrupt priority 1 f8h pt2 pcm2 pcm1 pcm0 pct3 pct2 pct1 pct0 00h p5# port 5 c4h adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 xxxxxxxxb c7 c6 c5 c4 c3 c2 c1 c0 p4# port 4 c0h cmt1 cmt0 cmsr5 cmsr4 cmsr3 cmsr2 cmsr1 cmsr0 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h a15 a14 a13 a12 a11 a10 a9 a8 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h sda scl rt2 t2 ct3i ct2i ct1i ct0i ffh 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh pcon# power control 87h smod wle gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 5 table 1. 8XC552 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value pwmp# pwm1# pwm0# pwm prescaler pwm register 1 pwm register 0 feh fdh fch 00h 00h 00h rte# reset/toggle enable efh tp47 tp46 rp45 rp44 rp43 rp42 rp41 rp40 00h sp stack pointer 81h 07h s0buf serial 0 data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 s0con* serial 0 control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h s1adr# serial 1 address dbh ??????? slave address ???????? gc 00h sidat# serial 1 data dah 00h s1sta# serial 1 status d9h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h df de dd dc db da d9 d8 sicon#* serial 1 control d8h cr2 ens1 sta st0 si aa cr1 cr0 00h ste# set enable eeh tg47 tg46 sp45 sp44 sp43 sp42 sp41 sp40 c0h th1 th0 tl1 tl0 tmh2# tml2# timer high 1 timer high 0 timer low 1 timer low 0 timer high 2 timer low 2 8dh 8ch 8bh 8ah edh ech 00h 00h 00h 00h 00h 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tm2con# timer 2 control eah t2is1 t2is0 t2er t2b0 t2p1 t2p0 t2ms1 t2ms0 00h cf ce cd cc cb ca c9 c8 tm2ir#* timer 2 int flag reg c8h t20v cmi2 cmi1 cmi0 cti3 cti2 cti1 cti0 00h t3# timer 3 ffh 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. ect0 bit symbol function ien1.7 et2 enable timer t2 overflow interrupt(s) ien1.6 ecm2 enable t2 comparator 2 interrupt ien1.5 ecm1 enable t2 comparator 1 interrupt ien1.4 ecm0 enable t2 comparator 0 interrupt ien1.3 ect3 enable t2 capture register 3 interrupt ien1.2 ect2 enable t2 capture register 2 interrupt ien1.1 ect1 enable t2 capture register 1 interrupt ien1.0 ect0 enable t2 capture register 0 interrupt su00755 ect1 ect2 ect3 ecm0 ecm1 ecm2 et2 0 1 2 3 4 5 6 7 (lsb) (msb) ien1 (e8h) figure 2. timer t2 interrupt enable register (ien1)
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 6 t2ms0 bit symbol function tm2con.7 tsis1 timer t2 16-bit overflow interrupt select tm2con.6 t2is0 timer t2 byte overflow interrupt select tm2con.5 t2er timer t2 external reset enable. when this bit is set, timer t2 may be reset by a rising edge on rt2 (p1.5). tm2con.4 t2bo timer t2 byte overflow interrupt flag tm2con.3 t2p1 tm2con.2 t2p0 tm2con.1 t2ms1 tm2con.0 t2ms0 su00756 t2ms1 t2p0 t2p1 t2bo t2er t2is0 t2is1 0 1 2 3 4 5 6 7 (lsb) (msb) tm2con (eah) timer t2 prescaler select t2p1 t2p0 timer t2 clock 0 0 clock source 0 1 clock source/2 1 0 clock source/4 1 1 clock source/8 timer t2 mode select 0 0 timer t2 halted (off) 0 1 t2 clock source = f osc /12 1 0 test mode; do not use 1 1 t2 clock source = pin t2 t2ms1 t2ms0 mode selected figure 3. t2 control register (tm2con) timer t2 extension: when a 12mhz oscillator is used, a 16-bit overflow on timer t2 occurs every 65.5, 131, 262, or 524 ms, depending on the prescaler division ratio; i.e., the maximum cycle time is approximately 0.5 seconds. in applications where cycle times are greater than 0.5 seconds, it is necessary to extend timer t2. this is achieved by selecting fosc/12 as the clock source (set t2ms0, reset t2ms1), setting the prescaler division ration to 1/8 (set t2p0, set t2p1), disabling the byte overflow interrupt (reset t2is0) and enabling the 16-bit overflow interrupt (set t2is1). the following software routine is written for a three-byte extension which gives a maximum cycle time of approximately 2400 hours. ovint: push acc ;save accumulator push psw ;save status inc timex1 ;increment first byte (low order) ;of extended timer mov a,timex1 jnz intex ;jump to intex if ;there is no overflow inc timex2 ;increment second byte mov a,timex2 jnz intex ;jump to intex if there is no overflow inc timex3 ;increment third byte (high order) intex: clr t2ov ;reset interrupt flag pop psw ;restore status pop acc ;restore accumulator reti ;return from interrupt timer t2, capture and compare logic: timer t2 is connected to four 16-bit capture registers and three 16-bit compare registers. a capture register may be used to capture the contents of timer t2 when a transition occurs on its corresponding input pin. a compare register may be used to set, reset, or toggle port 4 output pins at certain pre-programmable time intervals. the combination of timer t2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. timer t2 and the capture and compare logic are shown in figure 4. capture logic: the four 16-bit capture registers that timer t2 is connected to are: ct0, ct1, ct2, and ct3. these registers are loaded with the contents of timer t2, and an interrupt is requested upon receipt of the input signals ct0i, ct1i, ct2i, or ct3i. these input signals are shared with port 1. the four interrupt flags are in the timer t2 interrupt register (tm2ir special function register). if the capture facility is not required, these inputs can be regarded as additional external interrupt inputs. using the capture control register ctcon (see figure 5), these inputs may capture on a rising edge, a falling edge, or on either a rising or falling edge. the inputs are sampled during s1p1 of each cycle. when a selected edge is detected, the contents of timer t2 are captured at the end of the cycle.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 7 int int ct0 ct1 ct2 ct3 cti0 int ct0i cti1 ct1i cti2 ct2i cti3 ct3i 1/12 prescaler t2 counter 8-bit overflow interrupt 16-bit overflow interrupt external reset enable off f osc t2 rt2 t2er comp cmo (s) int comp cm1 (r) int comp cm2 (t) int p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 r r r r r r t t s s s s s s tg tg ste rte i/o port 4 s = set r = reset t = toggle tg = toggle status int tml2 = lower 8 bits tmh2 = higher 8 bits t2 sfr address: su00757 figure 4. block diagram of timer 2 measuring time intervals using capture registers: when a recurring external event is represented in the form of rising or falling edges on one of the four capture pins, the time between two events can be measured using timer t2 and a capture register. when an event occurs, the contents of timer t2 are copied into the relevant capture register and an interrupt request is generated. the interrupt service routine may then compute the interval time if it knows the previous contents of timer t2 when the last event occurred. with a 12mhz oscillator, timer t2 can be programmed to overflow every 524ms. when event interval times are shorter than this, computing the interval time is simple, and the interrupt service routine is short. for longer interval times, the timer t2 extension routine may be used. compare logic: each time timer t2 is incremented, the contents of the three 16-bit compare registers cm0, cm1, and cm2 are compared with the new counter value of timer t2. when a match is found, the corresponding interrupt flag in tm2ir is set at the end of the following cycle. when a match with cm0 occurs, the controller sets bits 0-5 of port 4 if the corresponding bits of the set enable register ste are at logic 1. when a match with cm1 occurs, the controller resets bits 0-5 of port 4 if the corresponding bits of the reset/toggle enable register rte are at logic 1 (see figure 6 for rte register function). if rte is a0o, then p4.n is not affected by a match between cm1 or cm2 and timer 2. when a match with cm2 occurs, the controller atoggleso bits 6 and 7 of port 4 if the corresponding bits of the rte are at logic 1. the port latches of bits 6 and 7 are not toggled. two additional flip-flops store the last operation, and it is these flip-flops that are toggled. thus, if the current operation is aset,o the next operation will be areseto even if the port latch is reset by software before the areseto operation occurs. the first atoggleo after a chip reset will set the port latch. the contents of these two flip-flops can be read at ste.6 and ste.7 (corresponding to p4.6 and p4.7, respectively). bits ste.6 and ste.7 are read only (see figure 7 for ste register function). a logic 1 indicates that the next toggle will set the port latch; a logic 0 indicates that the next toggle will reset the port latch. cm0, cm1, and cm2 are reset by the rst signal. the modified port latch information appears at the port pin during s5p1 of the cycle following the cycle in which a match occurred. if the port is modified by software, the outputs change during s1p1 of the following cycle. each port 4 bit can be set or reset by software at any time. a hardware modification resulting from a comparator match takes precedence over a software modification in the same cycle. when the comparator results require a aseto and a areseto at the same time, the port latch will be reset. timer t2 interrupt flag register tm2ir: eight of the nine timer t2 interrupt flags are located in special function register tm2ir (see figure 8). the ninth flag is tm2con.4. the ct0i and ct1i flags are set during s4 of the cycle in which the contents of timer t2 are captured. ct0i is scanned by the interrupt logic during s2, and ct1i is scanned during s3. ct2i and ct3i are set during s6 and are scanned during s4 and s5. the associated
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 8 interrupt requests are recognized during the following cycle. if these flags are polled, a transition at ct0i or ct1i will be recognized one cycle before a transition on ct2i or ct3i since registers are read during s5. the cmi0, cmi1, and cmi2 flags are set during s6 of the cycle following a match. cmi0 is scanned by the interrupt logic during s2; cmi1 and cmi2 are scanned during s3 and s4. a match will be recognized by the interrupt logic (or by polling the flags) two cycles after the match takes place. the 16-bit overflow flag (t2ov) and the byte overflow flag (t2bo) are set during s6 of the cycle in which the overflow occurs. these flags are recognized by the interrupt logic during the next cycle. special function register ip1 (figure 8) is used to determine the timer t2 interrupt priority. setting a bit high gives that function a high priority, and setting a bit low gives the function a low priority. the functions controlled by the various bits of the ip1 register are shown in figure 8. ctp0 bit symbol capture/interrupt on: ctcon.7 ctn3 capture register 3 triggered by a falling edge on ct3i ctcon.6 ctp3 capture register 3 triggered by a rising edge on ct3i ctcon.5 ctn2 capture register 2 triggered by a falling edge on ct2i ctcon.4 ctp2 capture register 2 triggered by a rising edge on ct2i ctcon.3 ctn1 capture register 1 triggered by a falling edge on ct1i ctcon.2 ctp1 capture register 1 triggered by a rising edge on ct1i ctcon.1 ctn0 capture register 0 triggered by a falling edge on ct0i ctcon.0 ctp0 capture register 0 triggered by a rising edge on ct0i su00758 ctn1 ctp1 ctn1 ctp2 ctn2 ctp3 ctn3 0 1 2 3 4 5 6 7 (lsb) (msb) ctcon (ebh) figure 5. capture control register (ctcon) rp40 bit symbol function rte.7 tp47 if a1o then p4.7 toggles on a match between cm1 and timer t2 rte.6 tp46 if a1o then p4.6 toggles on a match between cm1 and timer t2 rte.5 rp45 if a1o then p4.5 is reset on a match between cm1 and timer t2 rte.4 rp44 if a1o then p4.4 is reset on a match between cm1 and timer t2 rte.3 rp43 if a1o then p4.3 is reset on a match between cm1 and timer t2 rte.2 rp42 if a1o then p4.2 is reset on a match between cm1 and timer t2 rte.1 rp41 if a1o then p4.1 is reset on a match between cm1 and timer t2 rte.0 rp40 if a1o then p4.0 is reset on a match between cm1 and timer t2 su00759 ro41 rp42 rp43 rp44 rp45 tp46 tp47 0 1 2 3 4 5 6 7 (lsb) (msb) rte (efh) figure 6. reset/toggle enable register (rte) sp40 bit symbol function ste.7 tg47 toggle flip-flops ste.6 tg46 toggle flip-flops ste.5 sp45 if a1o then p4.5 is set on a match between cm0 and timer t2 ste.4 sp44 if a1o then p4.4 is set on a match between cm0 and timer t2 ste.3 sp43 if a1o then p4.3 is set on a match between cm0 and timer t2 ste.2 sp42 if a1o then p4.2 is set on a match between cm0 and timer t2 ste.1 sp41 if a1o then p4.1 is set on a match between cm0 and timer t2 ste.0 sp40 if a1o then p4.0 is set on a match between cm0 and timer t2 su00760 sp41 sp42 sp43 sp44 sp45 tg46 tg47 0 1 2 3 4 5 6 7 (lsb) (msb) ste (eeh) figure 7. set enable register (ste)
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 9 cti0 bit symbol function tm2ir.7 t2ov timer t2 16-bit overflow interrupt flag tm2ir.6 cmi2 cm2 interrupt flag tm2ir.5 cmi1 cm1 interrupt flag tm2ir.4 cmi0 cm0 interrupt flag tm2ir.3 cti3 ct3 interrupt flag tm2ir.2 cti2 ct2 interrupt flag tm2ir.1 cti1 ct1 interrupt flag tm2ir.0 cti0 ct0 interrupt flag su00761 cti1 cti2 cti3 cmi0 cmi1 cmi2 t2ov 0 1 2 3 4 5 6 7 (lsb) (msb) tm2ir (c8h) interrupt flag register (tm2ir) pct0 bit symbol function ip1.7 pt2 timer t2 overflow interrupt(s) priority level ip1.6 pcm2 timer t2 comparator 2 interrupt priority level ip1.5 pcm1 timer t2 comparator 1 interrupt priority level ip1.4 pcm0 timer t2 comparator 0 interrupt priority level ip1.3 pct3 timer t2 capture register 3 interrupt priority level ip1.2 pct2 timer t2 capture register 2 interrupt priority level ip1.1 pct1 timer t2 capture register 1 interrupt priority level ip1.0 pct0 timer t2 capture register 0 interrupt priority level pct1 pct2 pct3 pcm0 pcm1 pcm2 pt2 0 1 2 3 4 5 6 7 (lsb) (msb) ip1 (f8h) timer 2 interrupt priority register (ip1) figure 8. interrupt flag register (tm2ir) and timer t2 interrupt priority register (ip1) timer t3, the watchdog timer in addition to timer t2 and the standard timers, a watchdog timer is also incorporated on the 8XC552. the purpose of a watchdog timer is to reset the microcontroller if it enters erroneous processor states (possibly caused by electrical noise or rfi) within a reasonable period of time. an analogy is the adead man's handleo in railway locomotives. when enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer within a specified length of time known as the awatchdog interval.o watchdog circuit description: the watchdog timer (timer t3) consists of an 8-bit timer with an 11-bit prescaler as shown in figure 9. the prescaler is fed with a signal whose frequency is 1/12 the oscillator frequency (1mhz with a 12mhz oscillator). the 8-bit timer is incremented every ato seconds, where: t = 12 2048 1/f osc (= 1.5ms at f osc = 16mhz; = 1ms at f osc = 24mhz) if the 8-bit timer overflows, a short internal reset pulse is generated which will reset the 8XC552. a short output reset pulse is also generated at the rst pin. this short output pulse (3 machine cycles) may be destroyed if the rst pin is connected to a capacitor. this would not, however, affect the internal reset operation. watchdog operation is activated when external pin ew is tied low. when ew is tied low, it is impossible to disable the watchdog operation by software. how to operate the watchdog timer: the watchdog timer has to be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the watchdog timer will overflow and a system reset will be generated. the user program must therefore continually execute sections of code which reload the watchdog timer. the period of time elapsed between execution of these sections of code must never exceed the watchdog interval. when using a 16mhz oscillator, the watchdog interval is programmable between 1.5ms and 392ms. when using a 24mhz oscillator, the watchdog interval is programmable between 1ms and 255ms. in order to prepare software for watchdog operation, a programmer should first determine how long his system can sustain an erroneous processor state. the result will be the maximum watchdog interval. as the maximum watchdog interval becomes shorter, it becomes more difficult for the programmer to ensure that the user program always reloads the watchdog timer within the watchdog interval, and thus it becomes more difficult to implement watchdog operation. the programmer must now partition the software in such a way that reloading of the watchdog is carried out in accordance with the above requirements. the programmer must determine the execution times of all software modules. the effect of possible conditional branches, subroutines, external and internal interrupts must all be taken into account. since it may be very difficult to evaluate the execution times of some sections of code, the programmer should use worst case estimations. in any event, the programmer must make sure that the watchdog is not activated during normal operation.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 10 internal bus timer t3 (8-bit) load loaden prescaler (11-bit) clear f osc /12 ew wle clear pd loaden rst r rst v dd p internal reset internal bus write t3 pcon.4 pcon.1 overflow figure 9. watchdog timer the watchdog timer is reloaded in two stages in order to prevent erroneous software from reloading the watchdog. first pcon.4 (wle) must be set. the t3 may be loaded. when t3 is loaded, pcon.4 (wle) is automatically reset. t3 cannot be loaded if pcon.4 (wle) is reset. reload code may be put in a subroutine as it is called frequently. since timer t3 is an up-counter, a reload value of 00h gives the maximum watchdog interval (510ms with a 12mhz oscillator), and a reload value of 0ffh gives the minimum watchdog interval (2ms with a 12mhz oscillator). in the idle mode, the watchdog circuitry remains active. when watchdog operation is implemented, the power-down mode cannot be used since both states are contradictory. thus, when watchdog operation is enabled by tying external pin ew low, it is impossible to enter the power-down mode, and an attempt to set the power-down bit (pcon.1) will have no effect. pcon.1 will remain at logic 0. during the early stages of software development/debugging, the watchdog may be disabled by tying the ew pin high. at a later stage, ew may be tied low to complete the debugging process. watchdog software example: the following example shows how watchdog operation might be handled in a user program. ;at the program start: t3 equ 0ffh ;address of watchdog timer t3 pcon equ 087h ;address of pcon sfr watch-intv equ 156 ;watchdog interval (e.g., 2x100ms) ;to be inserted at each watchdog reload location within ;the user program: lcall watchdog ;watchdog service routine: watchdog: orl pcon,#10h ;set condition flag (pcon.4) mov t3,watch-inv ;load t3 with watchdog interval ret if it is possible for this subroutine to be called in an erroneous state, then the condition flag wle should be set at different parts of the main program. serial i/o the 8XC552 is equipped with two independent serial ports: sio0 and sio1. sio0 is a full duplex uart port and is identical to the 80c51 serial port. sio1 accommodates the i 2 c bus. sio0: sio0 is a full duplex serial i/o port identical to that on the 80c51. its operation is the same, including the use of timer 1 as a baud rate generator. sio1, i 2 c serial i/o: the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: bidirectional data transfer between masters and slaves multimaster bus (no central master) arbitration between simultaneously transmitting masters without corruption of serial data on the bus serial clock synchronization allows devices with different bit rates to communicate via one serial bus serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer the i 2 c bus may be used for test and diagnostic purposes the output latches of p1.6 and p1.7 must be set to logic 1 in order to enable sio1. the 8XC552 on-chip i 2 c logic provides a serial interface that meets the i 2 c bus specification and supports all transfer modes (other than the low-speed mode) from and to the i 2 c bus. the sio1 logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register (s1sta) reflects the status of sio1 and the i 2 c bus.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 11 the cpu interfaces to the i 2 c logic via the following four special function registers: s1con (sio1 control register), s1sta (sio1 status register), s1dat (sio1 data register), and s1adr (sio1 slave address register). the sio1 logic interfaces to the external i 2 c bus via two port 1 pins: p1.6/scl (serial clock line) and p1.7/sda (serial data line). a typical i 2 c bus configuration is shown in figure 10, and figure 11 shows how a data transfer is accomplished on the bus. depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c bus: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a anot acknowledgeo is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. modes of operation: the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode: serial data output through p1.7/sda while p1.6/scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case the data direction bit (r/w ) will be logic 0, and we say that a awo is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode: the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case the data direction bit (r/w ) will be logic 1, and we say that an aro is transmitted. thus the first byte transmitted is sla+r. serial data is received via p1.7/sda while p1.6/scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received through p1.7/sda and p1.6/scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via p1.7/sda while the serial clock is input through p1.6/scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. sio1 implementation and operation: figure 12 shows how the on-chip i 2 c bus interface is implemented, and the following text describes the individual blocks. i nput f ilters and o utput s tages the input filters have i 2 c compatible input levels. if the input voltage is less than 1.5v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0v, the input logic level is interpreted as 1. input signals are synchronized with the internal clock (f osc /4), and spikes shorter than three oscillator periods are filtered out. the output stages consist of open drain transistors that can sink 3ma at v out < 0.4v. these open drain outputs do not have clamping diodes to v dd . thus, if the device is connected to the i 2 c bus and v dd is switched off, the i 2 c bus is not affected. a ddress r egister, s 1 adr this 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call address (00h) recognition. c omparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in s1adr). it also compares the first received 8-bit byte with the general call address (00h). if an equality is found, the appropriate status bits are set and an interrupt is requested. s hift r egister, s 1 dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 12 v dd other device with i 2 c interface 8XC552 other device with i 2 c interface p1.7/sda p1.6/scl sda scl i 2 c bus r p r p figure 10. typical i 2 c bus configuration scl start condition s sda p/s msb acknowledgment signal from receiver clock line held low while interrupts are serviced 1 2 7 8 9 1 2 38 ack 9 ack repeated if more bytes are transferred acknowledgment signal from receiver slave address r/w direction bit stop condition repeated start condition figure 11. data transfer on the i 2 c bus
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 13 f osc /4 internal bus address register comparator shift register control register status register arbitration & sync logic timing & control logic serial clock generator ack status decoder timer 1 overflow interrupt 8 8 8 8 s1sta status bits s1con s1dat input filter output stage p1.7 input filter output stage p1.6 p1.6/scl p1.7/sda s1adr figure 12. i 2 c bus serial interface block diagram
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 14 ack 1. another device transmits identical serial data. sda 1 234 89 scl (1) (1) (2) (3) 2. another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lost, and sio1 enters the slave receiver mode. 3. sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. figure 13. arbitration procedure (1) scl (3) (1) sda mark duration space duration (2) 1. another service pulls the scl line low before the sio1 amarko duration is complete. the serial clock generator is immediately reset and commences with the aspaceo duration by pulling scl low. 2. another device still pulls the scl line low after sio1 releases scl. the serial clock generator is forced into the wait state until the scl line is released. 3. the scl line is released, and the serial clock generator commences with the mark duration. figure 14. serial clock synchronization a rbitration and s ynchronization l ogic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a anot acknowledge: (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. figure 13 shows the arbitration procedure. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the amarko duration is determined by the device that generates the shortest amarks,o and the aspaceo duration is determined by the device that generates the longest aspaces.o figure 14 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. s erial c lock g enerator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. the programmable output clock frequencies are: f osc /120, f osc /9600, and the timer 1 overflow rate divided by eight. the output clock
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 15 pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. t iming and c ontrol the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the i 2 c bus status. c ontrol r egister, s 1 con this 7-bit special function register is used by the microcontroller to control the following sio1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. s tatus d ecoder and s tatus r egister the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code is sufficient for most of the service routines (see the software example in this section). the four sio1 special function registers: the microcontroller interfaces to sio1 via four special function registers. these four sfrs (s1adr, s1dat, s1con, and s1sta) are described individually in the following sections. the address register, s1adr: the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontroller's own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. s1adr (dbh) xgc 7 65 432 10 own slave address x xx xx x the most significant bit corresponds to the first bit received from the i 2 c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. the data register, s1dat: s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. s1dat (dah) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 7 65 43 2 1 0 shift direction sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. figure 15 shows how data in s1dat is serially transferred to and from the sda line. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer (bsd7) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, bsd7 is loaded with the content of s1dat.7, which is the first bit to be transmitted to the sda line (see figure 16). after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat. internal bus 8 bsd7 s1dat ack scl sda shift pulses figure 15. serial input/output configuration
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 16 the control register, s1con: the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ens1 = a0o. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 cr2 ens 1, the sio 1 e nable b it ens1 = a0o: when ens1 is a0o, the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the anot addressedo slave state, and the sto bit in s1con is forced to a0o. no other bits are affected. p1.6 and p1.7 may be used as open drain i/o ports. ens1 = a1o: when ens1 is a1o, sio1 is enabled. the p1.6 and p1.7 port latches must be set to logic 1. ens1 should not be used to temporarily release sio1 from the i2c bus since, when ens1 is reset, the i2c bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text). in the following text, it is assumed that ens1 = a1o. sta , the start f lag sta = a1o: when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i2c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal serial clock generator. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 transmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = a0o: when the sta bit is reset, no start condition or repeated start condition will be generated. sto , the stop f lag sto = a1o: when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the defined anot addressedo slave receiver mode. the sto flag is automatically cleared by hardware. if the sta and sto bits are both set, the a stop condition is transmitted to the i 2 c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = a0o: when the sto bit is reset, no stop condition will be generated. si , the s erial i nterrupt f lag si = a1o: when the si flag is set, then, if the ea and es1 (interrupt enable register) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = a0o: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. aa , the a ssert a cknowledge f lag aa = a1o: if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: the aown slave addresso has been received the general call address has been received while the general call bit (gc) in s1adr is set a data byte has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode aa = a0o: if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: a data has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 20). when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. cr 0, cr 1, and cr 2, the c lock r ate b its these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 2. a 12.5khz bit rate may be used by devices that interface to the i 2 c bus via standard i/o port lines which are software driven and slow. 100khz is usually the maximum bit rate and can be derived from a 16mhz, 12mhz, or a 6mhz oscillator. a variable bit rate (0.5khz to 62.5khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in table 2 are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100khz.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 17 the status register, s1sta: s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = a1o). a valid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. more information on sio1 operating modes: the four operating modes are: master transmitter master receiver slave receiver slave transmitter data transfers in each mode of operation are shown in figures 1737. these figures contain the following abbreviations: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 17-37, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the s1sta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables 3-7. master transmitter mode: in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 17). before the master transmitter mode can be entered, s1con must be initialized as follows: s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 7 6543210 1000x bit rate bit rate cr0, cr1, and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i 2 c bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla+w). the si bit in s1con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 3. after a repeated start condition (state 10h). sio1 may switch to the master receiver mode by loading s1dat with sla+r).
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 18 shift in sda scl d7 d6 d5 d4 d3 d2 d1 d0 a shift ack & s1dat ack (2) (2) (2) (2) (2) (2) (2) (2) a (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) s1dat shift bsd7 bsd7 d7 d6 d5 d4 d3 d2 d1 d0 (3) loaded by the cpu (1) valid data in s1dat (2) shifting data in s1dat and ack (3) high level on sda shift out figure 16. shift-in and shift-out timing table 2. serial clock rates bit frequency (khz) at f osc cr2 cr1 cr0 6mhz 12mhz 16mhz f osc divided by 0 0 0 23 47 63 256 0 0 1 27 54 71 224 0 1 0 31 63 83 192 0 1 1 37 75 100 160 1 0 0 6.25 12.5 17 960 1 0 1 50 100 120 1 1 0 100 60 1 1 1 0.25 < 62.5 0.5 < 62.5 0.67 < 56 96 (256 reload value timer 1) (reload value range: 0 254 in mode 2)
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 19 ???????? ???????? ??? ??? ??? ??? ??? ??? s sla wa a data p ??????? ??????? ??????? s sla w ??? ??? a p ??? ??? ??? a p 08h 18h 28h ??? ??? r 38h a or a other mst continues a or a other mst continues 38h 30h 20h 68h 78h 80h other mst continues a mt 10h to mst/rec mode entry = mr to corresponding states in slave mode successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 3. data figure 17. format and states in the master transmitter mode
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 20 ???????? ???????? ??? ??? s sla r a data p ??????? ??????? ??????? s sla r ??? ??? a p 08h 40h 50h ??? ??? w 38h a or a other mst continues other mst continues 38h 48h 68h 78h 80h other mst continues a mr 10h to mst/trx mode entry = mt to corresponding states in slave mode successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave ???? ???? ???? ???? ???? n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 4. ??? ??? a ???? ???? data ??? ??? a 58h ??? ??? ??? a ?? ?? data a figure 18. format and states in the master receiver mode
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 21 ??????? ??????? ??? ??? ???? ???? ??? ??? s sla wa a data p or s a 60h 80h 68h reception of the own slave address and one or more data bytes all are acknowledged. last data byte received is not acknowledged arbitration lost as mst and addressed as slave reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 5. data a sla ??? ??? data 80h a0h ??? ??? ??? a 88h p or s ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? general call aa data p or s 70h 90h 78h a data 90h a0h a 98h p or s a figure 19. format and states in the slave receiver mode
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 22 ???????? ???????? ???????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? s sla r a data p or s b0h a8h b8h reception of the own slave address and transmission of one or more data bytes a data a c0h ???? ???? ?? ?? n any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 6. data a ??? ??? ??? all a1os ??? ??? ??? a a ???? ???? from master to slave from slave to master c8h p or s last data byte transmitted. switched to not addressed slave (aa bit in s1con = a0o arbitration loast as mst and addressed as slave figure 20. format and states of the slave transmitter mode master receiver mode: in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 18). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 4. ens1, cr1, and cr0 are not affected by the serial transfer and are not referred to in table 4. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla+w. slave receiver mode: in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 19). to initiate the slave receiver mode, s1adr and s1con must be loaded as follows: s1adr (dbh) xgc 7 65 432 1 0 own slave address x xx xx x the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb (gc) is set, sio1 will respond to the general call address (00h); otherwise it ignores the general call address. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 x1 0001x x cr2 cr0, cr1, and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowledge its own slave address or the general call address. sta, sto, and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a0o (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 5. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 23 table 3. master transmitter mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmitted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmitted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in s1dat has been transmitted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in s1dat has been transmitted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r/w or data bytes no s1dat action or no s1dat action 0 1 0 0 0 0 x x i 2 c bus will be released; not addressed slave will be entered a start condition will be transmitted when the bus becomes free
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 24 table 4. master receiver mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa 08h a start condition has been transmitted load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or no s1dat action 0 1 0 0 0 0 x x i 2 c bus will be released; sio1 will enter a slave mode a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has been received no s1dat action or no s1dat action 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 48h sla+r has been transmitted; not ack has been received no s1dat action or no s1dat action or no s1dat action 1 0 1 0 1 1 0 0 0 x x x repeated start condition will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 58h data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start condition will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 25 table 5. slave receiver mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa 60h own sla+w has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has been received, ack returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 70h general call address (00h) has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received, ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 80h previously addressed with own slv address; data has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 88h previously addressed with own sla; data byte has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data byte has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 98h previously addressed with general call; data byte has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 26 table 5. slave receiver mode (continued) status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx no stdat action or no stdat action or no stdat action or no stdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. table 6. slave transmitter mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa a8h own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been received load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack has been received no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been transmitted (aa = 0); ack has been received no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 27 slave transmitter mode: in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 20). data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a1o (r) for sio1 to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 6. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus. miscellaneous states: there are two s1sta codes that do not correspond to a defined sio1 hardware state (see table 7). these are discussed below. s1sta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h: this status code indicates that a bus error has occurred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio1 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the anot addressedo slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is not transmitted). some special cases: the sio1 hardware has facilities to handle the following special cases that may occur during a serial transfer: simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 21). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i 2 c bus before generating a repeated start condition itself, it will release the bus, and no interrupt request is generated. if another master frees the bus by generating a stop condition, sio1 will transmit a normal start condition (state 08h), and a retry of the total serial data transfer can commence. d ata t ransfer a fter l oss of a rbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 13). loss of arbitration is indicated by the following states in s1sta; 38h, 68h, 78h, and b0h (see figures 17 and 18). if the sta flag in s1con is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. f orced a ccess to the i 2 c b us in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware (see figure 22). i 2 c b us o bstructed by a l ow l evel on scl or sda an i 2 c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line (see figure 23). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i 2 c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. b us e rror a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 7.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 28 table 7. miscellaneous states status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa f8h no relevant state information available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an undefined state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not addressed slv mode. sto is reset. s 08h sla w a data a s other mst continues p s sla 18h 28h 08h other master sends repeated start condition earlier retry figure 21. simultaneous repeated start conditions from 2 masters
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 29 sta flag sto flag time limit sda line scl line start condition figure 22. forced access to a busy i 2 c bus sta flag start condition (1) unsuccessful attempt to send a start condition (2) sda line released (3) successful attempt to send a start condition; state 08h is entered sda line scl line (1) (1) (2) (3) figure 23. recovering from a bus obstruction caused by a low level on sda
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 30 software examples of sio1 service routines: this section consists of a software example for: initialization of sio1 after a reset entering the sio1 interrupt routine the 26 state service routines for the master transmitter mode master receiver mode slave receiver mode slave transmitter mode i nitialization in the initialization routine, sio1 is enabled for both master and slave modes. for each mode, a number of bytes of internal data ram are allocated to the sio to act as either a transmission or reception buffer. in this example, 8 bytes of internal data ram are reserved for different purposes. the data memory map is shown in figure 24. the initialization routine performs the following functions: s1adr is loaded with the part's own slave address and the general call bit (gc) p1.6 and p1.7 bit latches are loaded with logic 1s ram location hadd is loaded with the high-order address byte of the service routines the sio1 interrupt enable and interrupt priority bits are set the slave mode is enabled by simultaneously setting the ens1 and aa bits in s1con and the serial clock frequency (for master modes) is defined by loading cr0 and cr1 in s1con. the master routines must be started in the main program. the sio1 hardware now begins checking the i 2 c bus for its own slave address and general call. if the general call or the own slave address is detected, an interrupt is requested and s1sta is loaded with the appropriate state information. the following text describes a fast method of branching to the appropriate service routine. sio 1 i nterrupt r outine when the sio1 interrupt is entered, the psw is first pushed on the stack. then s1sta and hadd (loaded with the high-order address byte of the 26 service routines by the initialization routine) are pushed on to the stack. s1sta contains a status code which is the lower byte of one of the 26 service routines. the next instruction is ret, which is the return from subroutine instruction. when this instruction is executed, the high and low order address bytes are popped from stack and loaded into the program counter. the next instruction to be executed is the first instruction of the state service routine. seven bytes of program code (which execute in eight machine cycles) are required to branch to one of the 26 state service routines. si push psw save psw push s1sta push status code (low order address byte) push hadd push high order address byte ret jump to state service routine the state service routines are located in a 256-byte page of program memory. the location of this page is defined in the initialization routine. the page can be located anywhere in program memory by loading data ram register hadd with the page number. page 01 is chosen in this example, and the service routines are located between addresses 0100h and 01ffh. t he s tate s ervice r outines the state service routines are located 8 bytes from each other. eight bytes of code are sufficient for most of the service routines. a few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code. each state routine is part of the sio1 interrupt routine and handles one of the 26 states. it ends with a reti instruction which causes a return to the main program. m aster t ransmitter and m aster r eceiver m odes the master mode is entered in the main program. to enter the master transmitter mode, the main program must first load the internal data ram with the slave address, data bytes, and the number of data bytes to be transmitted. to enter the master receiver mode, the main program must first load the internal data ram with the slave address and the number of data bytes to be received. the r/w bit determines whether sio1 operates in the master transmitter or master receiver mode. master mode operation commences when the sta bit in s1cion is set by the setb instruction and data transfer is controlled by the master state service routines in accordance with table 3, table 4, figure 17, and figure 18. in the example below, 4 bytes are transferred. there is no repeated start condition. in the event of lost arbitration, the transfer is restarted when the bus becomes free. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. if a slave device returns a not acknowledge, a stop condition is generated. a repeated start condition can be included in the serial transfer if the sta flag is set instead of the sto flag in the state service routines vectored to by status codes 28h and 58h. additional software must be written to determine which data is transferred after a repeated start condition. s lave t ransmitter and s lave r eceiver m odes after initialization, sio1 continually tests the i 2 c bus and branches to one of the slave state service routines if it detects its own slave address or the general call address (see table 5, table 6, figure 19, and figure 20). if arbitration was lost while in the master mode, the master mode is restarted after the current transfer. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. in the slave receiver mode, a maximum of 8 received data bytes can be stored in the internal data ram. a maximum of 8 bytes ensures that other ram locations are not overwritten if a master sends more bytes. if more than 8 bytes are transmitted, a not acknowledge is returned, and sio1 enters the not addressed slave receiver mode. a maximum of one received data byte can be stored in the internal data ram after a general call address is detected. if more than one byte is transmitted, a not acknowledge is returned and sio1 enters the not addressed slave receiver mode. in the slave transmitter mode, data to be transmitted is obtained from the same locations in the internal data ram that were previously loaded by the main program. after a not acknowledge has been returned by a master receiver device, sio1 enters the not addressed slave mode. a dapting the s oftware for d ifferent a pplications the following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. if one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked. this example does not include any time-out routines. in the slave modes, time-out routines are not very useful since, in these modes, sio1 behaves essentially as a passive device. in the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. this time period is defined by the system connected to the i 2 c bus.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 31 db s1adr gc s1dat 0 0 cr0 cr! si 0 aa st0 sta cr2 ens1 special function registers 53 backup numbytmst internal data ram s1sta s1con psw da d9 d8 d0 ps1 ipo b8 ien0 ab es1 ea p1.7 p1.6 p1 90 80 7f original value of numbytmst number of bytes as master 52 sla sla+r/w to be transmitted to sla 51 hadd higher address byte interrupt routine 50 slave transmitter data ram 4f std 48 slave receiver data ram srd 40 master receiver data ram mrd 38 master transmitter data ram mtd 30 19 r1 r0 18 00 figure 24. sio1 data memory map
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 32 !******************************************************************************************************** ! si01 equate list !******************************************************************************************************** !******************************************************************************************************** ! locations of the si01 special function registers !******************************************************************************************************** 00d8 s1con 0xd8 00d9 s1sta 0xd9 00da s1dat 0xda 00db s1adr 0xdb 00a8 ien0 0xa8 00b8 ip0 02b8 !******************************************************************************************************** ! bit locations !******************************************************************************************************** 00dd sta 0xdd ! sta bit in s1con 00bd si01hp 0xbd ! ip0, si01 priority bit !******************************************************************************************************** ! immediate data to write into register s1con !******************************************************************************************************** 00d5 ens1_notsta_sto_notsi_aa_cr0 0xd5 ! generates stop ! (cr0 = 100khz) 00c5 ens1_notsta_notsto_notsi_aa_cr0 0xc5 ! releases bus and ! ack 00c1 ens1_notsta_notsto_notsi_notaa_cr0 0xc1 ! releases bus and ! not ack 00e5 ens1_sta_notsto_notsi_aa_cr0 0xe5 ! releases bus and ! set sta !******************************************************************************************************** ! general immediate data !******************************************************************************************************** 0031 ownsla 0x31 ! own sla+general call ! must be written into s1adr 00a0 ensi01 0xa0 ! ea+es1, enable sio1 interrupt ! must be written into ien0 0001 pag1 0x01 ! select pag1 as hadd 00c0 slaw 0xc0 ! sla+w to be transmitted 00c1 slar 0xc1 ! sla+r to be transmitted 0018 selrb3 0x18 ! select register bank 3 !******************************************************************************************************** ! locations in data ram !******************************************************************************************************** 0030 mtd 0x30 ! mst/trx/data base address 0038 mrd 0x38 ! mst/rec/data base address 0040 srd 0x40 ! slv/rec/data base address 0048 std 0x48 ! slv/trx/data base address 0053 backup 0x53 ! backup from numbytmst ! to restore numbytmst in case ! of an arbitration loss. 0052 numbytmst 0x52 ! number of bytes to transmit ! or receive as mst. 0051 sla 0x51 ! contains sla+r/w to be ! transmitted. 0050 hadd 0x50 ! high address byte for state 0 ! till state 25.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 33 !******************************************************************************************************** ! initialization routine ! example to initialize iic interface as slave receiver or slave transmitter and ! start a master transmit or a master receive function. 4 bytes will be transmitted or received. !******************************************************************************************************** .sect strt .base 0x00 0000 4100 ajmp init ! reset .sect initial .base 0x200 0200 75db31 init: mov s1adr,#ownsla ! load own sla + enable ! general call recognition 0203 d296 setb p1(6) ! p1.6 high level. 0205 d297 setb p1(7) ! p1.7 high level. 0207 755001 mov hadd,#pag1 020a 43a8a0 orl ien0,#ensi01 ! enable si01 interrupt 020d c2bd clr si01hp ! si01 interrupt low priority 020f 75d8c5 mov s1con, #ens1_notsta_notsto_notsi_aa_cr0 ! initialize slv funct. !******************************************************************************************************** ! ! start master transmit function ! 0212 755204 mov numbytmst,#0x4 ! transmit 4 bytes. 0215 7551c0 mov sla,#slaw ! sla+w, transmit funct. 0218 d2dd setb sta ! set sta in s1con ! ! start master receive function ! 021a 755204 mov numbytmst,#0x4 ! receive 4 bytes. 021d 7551c1 mov sla,#slar ! sla+r, receive funct. 0220 d2dd setb sta ! set sta in s1con !******************************************************************************************************** ! si01 interrupt routine !******************************************************************************************************** .sect intvec ! si01 interrupt vector .base 0x00 ! s1sta and hadd are pushed onto the stack. ! they serve as return address for the ret instruction. ! the ret instruction sets the program counter to address hadd, ! s1sta and jumps to the right subroutine. 002b c0d0 push psw ! save psw 002d c0d9 push s1sta 002f c050 push hadd 0031 22 ret ! jmp to address hadd,s1sta. ! ! state : 00, bus error. ! action : enter not addressed slv mode and release bus. sto reset. ! .sect st0 .base 0x100 0100 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si ! set sto,aa 0103 d0d0 pop psw 0105 32 reti
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 34 !******************************************************************************************************** !******************************************************************************************************** ! master state service routines !******************************************************************************************************** ! state 08 and state 10 are both for mst/trx and mst/rec. ! the r/w bit decides whether the next state is within ! mst/trx mode or within mst/rec mode. !******************************************************************************************************** ! ! state : 08, a, start condition has been transmitted. ! action : sla+r/w are transmitted, ack bit is received. ! .sect mts8 .base 0x108 0108 8551da mov s1dat,sla ! load sla+r/w 010b 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 ! ! state : 10, a repeated start condition has been ! transmitted. ! action : sla+r/w are transmitted, ack bit is received. ! .sect mts10 .base 0x110 0110 8551da mov s1dat,sla ! load sla+r/w 0113 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 .sect ibase1 .base 0xa0 00a0 75d018 initbase1: mov psw,#selrb3 00a3 7930 mov r1,#mtd 00a5 7838 mov r0,#mrd 00a7 855253 mov backup,numbytmst ! save initial value 00aa d0d0 pop psw 00ac 32 reti !******************************************************************************************************** !******************************************************************************************************** ! master transmitter state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 18, previous state was state 8 or state 10, sla+w have been transmitted, ! ack has been received. ! action : first data is transmitted, ack bit is received. ! .sect mts18 .base 0x118 0118 75d018 mov psw,#selrb3 011b 87da mov s1dat,@r1 011d 01b5 ajmp con
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 35 ! ! state : 20, sla+w have been transmitted, not ack has been received ! action : transmit stop condition. ! .sect mts20 .base 0x120 0120 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0123 d0d0 pop psw 0125 32 reti ! ! state : 28, data of s1dat have been transmitted, ack received. ! action : if transmitted data is last data then transmit a stop condition, ! else transmit next data. ! .sect mts28 .base 0x128 0128 d55285 djnz numbytmst,notldat1 ! jmp if not last data 012b 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si, set aa 012e 01b9 ajmp retmt .sect mts28sb .base 0x0b0 00b0 75d018 notldat1: mov psw,#selrb3 00b3 87da mov s1dat,@r1 00b5 75d8c5 con: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00b8 09 inc r1 00b9 d0d0 retmt : pop psw 00bb 32 reti ! ! state : 30, data of s1dat have been transmitted, not ack received. ! action : transmit a stop condition. ! .sect mts30 .base 0x130 0130 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0133 d0d0 pop psw 0135 32 reti ! ! state : 38, arbitration lost in sla+w or data. ! action : bus is released, not addressed slv mode is entered. ! a new start condition is transmitted when the iic bus is free again. ! .sect mts38 .base 0x138 0138 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 013b 855352 mov numbytmst,backup 013e 01b9 ajmp retmt
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 36 !******************************************************************************************************** !******************************************************************************************************** ! master receiver state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 40, previous state was state 08 or state 10, ! sla+r have been transmitted, ack received. ! action : data will be received, ack returned. ! .sect mts40 .base 0x140 0140 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr sta, sto, si set aa 0143 d0d0 pop psw 32 reti ! ! state : 48, sla+r have been transmitted, not ack received. ! action : stop condition will be generated. ! .sect mts48 .base 0x148 0148 75d8d5 stop: mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 014b d0d0 pop psw 014d 32 reti ! ! state : 50, data have been received, ack returned. ! action : read data of s1dat. ! data will be received, if it is last data then not ack will be returned else ack will be returned. ! .sect mrs50 .base 0x150 0150 75d018 mov psw,#selrb3 0153 a6da mov @r0,s1dat ! read received data 0155 01c0 ajmp rec1 .sect mrs50s .base 0xc0 00c0 d55205 rec1: djnz numbytmst,notldat2 00c3 75d8c1 mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00c6 8003 sjmp retmr 00c8 75d8c5 notldat2: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00cb 08 retmr: inc r0 00cc d0d0 pop psw 00ce 32 reti ! ! state : 58, data have been received, not ack returned. ! action : read data of s1dat and generate a stop condition. ! .sect mrs58 .base 0x158 0158 75d018 mov psw,#selrb3 015b a6da mov @r0,s1dat 015d 80e9 sjmp stop
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 37 !******************************************************************************************************** !******************************************************************************************************** ! slave receiver state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 60, own sla+w have been received, ack returned. ! action : data will be received and ack returned. ! .sect srs60 .base 0x160 0160 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0163 75d018 mov psw,#selrb3 0166 01d0 ajmp initsrd .sect insrd .base 0xd0 00d0 7840 initsrd: mov r0,#srd 00d2 7908 mov r1,#8 00d4 d0d0 pop psw 00d6 32 reti ! ! state : 68, arbitration lost in sla and r/w as mst ! own sla+w have been received, ack returned ! action : data will be received and ack returned. ! sta is set to restart mst mode after the bus is free again. ! .sect srs68 .base 0x168 0168 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 016b 75d018 mov psw,#selrb3 016e 01d0 ajmp initsrd ! ! state : 70, general call has been received, ack returned. ! action : data will be received and ack returned. ! .sect srs70 .base 0x170 0170 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0173 75d018 mov psw,#selrb3 ! initialize srd counter 0176 01d0 ajmp initsrd ! ! state : 78, arbitration lost in sla+r/w as mst. ! general call has been received, ack returned. ! action : data will be received and ack returned. ! sta is set to restart mst mode after the bus is free again. ! .sect srs78 .base 0x178 0178 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 017b 75d018 mov psw,#selrb3 ! initialize srd counter 017e 01d0 ajmp initsrd
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 38 ! ! state : 80, previously addressed with own sla. data received, ack returned. ! action : read data. ! if received data was the last ! then superfluous data will be received and not ack returned else next data will be received and ack returned. ! .sect srs80 .base 0x180 0180 75d018 mov psw,#selrb3 0183 a6da mov @r0,s1dat ! read received data 0185 01d8 ajmp rec2 .sect srs80s .base 0xd8 00d8 d906 rec2: djnz r1,notldat3 00da 75d8c1 ldat: mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00dd d0d0 pop psw 00df 32 reti 00e0 75d8c5 notldat3: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00e3 08 inc r0 00e4 d0d0 retsr: pop psw 00e6 32 reti ! ! state : 88, previously addressed with own sla. data received not ack returned. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01. ! .sect srs88 .base 0x188 0188 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 018b 01e4 ajmp retsr ! ! state : 90, previously addressed with general call. ! data has been received, ack has been returned. ! action : read data. after general call only one byte will be received with ack ! the second data will be received with not ack. ! data will be received and not ack returned. ! .sect srs90 .base 0x190 0190 75d018 mov psw,#selrb3 0193 a6da mov @r0,s1dat ! read received data 0195 01da ajmp ldat ! ! state : 98, previously addressed with general call. ! data has been received, not ack has been returned. ! action : no save of data, enter not addressed slv mode. recognition of own sla. general call recognized, if s1adr. 01. ! .sect srs98 .base 0x198 0198 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 019b d0d0 pop psw 019d 32 reti
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 39 ! ! state : a0, a stop condition or repeated start has been received, ! while still addressed as slv/rec or slv/trx. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01. ! .sect srsa0 .base 0x1a0 01a0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01a3 d0d0 pop psw 01a5 32 reti !******************************************************************************************************** !******************************************************************************************************** ! slave transmitter state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : a8, own sla+r received, ack returned. ! action : data will be transmitted, a bit received. ! .sect stsa8 .base 0x1a8 01a8 8548da mov s1dat,std ! load data in s1dat 01ab 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01ae 01e8 ajmp initbase2 .sect ibase2 .base 0xe8 00e8 75d018 initbase2: mov psw,#selrb3 00eb 7948 mov r1, #std 00ed 09 inc r1 00ee d0d0 pop psw 00f0 32 reti ! ! state : b0, arbitration lost in sla and r/w as mst. own sla+r received, ack returned. ! action : data will be transmitted, a bit received. ! sta is set to restart mst mode after the bus is free again. ! .sect stsb0 .base 0x1b0 01b0 8548da mov s1dat,std ! load data in s1dat 01b3 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 01b6 01e8 ajmp initbase2
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 40 ! ! state : b8, data has been transmitted, ack received. ! action : data will be transmitted, ack bit is received. ! .sect stsb8 .base 0x1b8 01b8 75d018 mov psw,#selrb3 01bb 87da mov s1dat,@r1 01bd 01f8 ajmp scon .sect scn .base 0xf8 00f8 75d8c5 scon: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00fb 09 inc r1 00fc d0d0 pop psw 00fe 32 reti ! ! state : c0, data has been transmitted, not ack received. ! action : enter not addressed slv mode. ! .sect stsc0 .base 0x1c0 01c0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01c3 d0d0 pop psw 01c5 32 reti ! ! state : c8, last data has been transmitted (aa=0), ack received. ! action : enter not addressed slv mode. ! .sect stsc8 .base 0x1c8 01c8 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01cb d0d0 pop psw 01cd 32 reti !******************************************************************************************************** !******************************************************************************************************** ! end of si01 interrupt routine !******************************************************************************************************** !********************************************************************************************************
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 41 reset circuitry the reset circuitry for the 8XC552 is connected to the reset pin rst. a schmitt trigger is used at the input for noise rejection (see figure 25). the output of the schmitt trigger is sampled by the reset circuitry every machine cycle. a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. the cpu responds by executing an internal reset. during reset, ale and psen output a high level. in order to perform a correct reset, this level must not be affected by external elements. the rst line can also be pulled high internally by a pull-up transistor activated by the watchdog timer t3. the length of the output pulse from t3 is 3 machine cycles. a pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. note that the short reset pulse from timer t3 cannot discharge the power-on reset capacitor (see figure 26). consequently, when the watchdog timer is also used to set external devices, this capacitor arrangement should not be connected to the rst pin, and a different circuit should be used to perform the power-on reset operation. a timer t3 overflow, if enabled, will force a reset condition to the 8XC552 by an internal connection, whether the output rst is tied low or not. v dd r rst rst schmitt trigger reset circuitry on-chip resistor overflow timer t3 figure 25. on-chip reset configuration r rst v dd v dd + 2.2 m f 8XC552 rst figure 26. power-on reset the internal reset is executed during the second cycle in which rst is high and is repeated every cycle until rst goes low. it leaves the internal registers as follows: resgister content acc 0000 0000 adcon xx00 0000 adch xxxx xxxx b 0000 0000 cml0-cml2 0000 0000 cmh0-cmh2 0000 0000 ctcon 0000 0000 ctl0-ctl3 xxxx xxxx cth0-cth3 xxxx xxxx dpl 0000 0000 dph 0000 0000 ien0 0000 0000 ien1 0000 0000 ip0 0000 0000 ip1 0000 0000 pch 0000 0000 pcl 0000 0000 pcon 0xx0 0000 psw 0000 0000 pwm0 0000 0000 pwm1 0000 0000 pwmp 0000 0000 p0-p4 1111 1111 ps xxxx xxxx rte 0000 0000 s0buf xxxx xxxx s0con 0000 0000 s1adr 0000 0000 s1con 0000 0000 s1dat 0000 0000 s1sta 1111 1000 sp 0000 0111 ste 1100 0000 tcon 0000 0000 th0, th1 0000 0000 tmh2 0000 0000 tl0, tl1 0000 0000 tml2 0000 0000 tmod 0000 0000 tm2con 0000 0000 tm2ir 0000 0000 t3 0000 0000 the internal ram is not affected by reset. at power-on, the ram content is indeterminate.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 42 interrupts the 8XC552 has fifteen interrupt sources, each of which can be assigned one of two priority levels, as shown in figure 27. the five interrupt sources common to the 80c51 are the external interrupts (int0 and int1 ), the timer 0 and timer 1 interrupts (it0 and it1), and the serial i/o interrupt (ri or ti). in the 8XC552, the standard serial interrupt is called sio0. since the subsystems which create these interrupts are identical on both parts, their functionality is likewise identical. the only differences are the locations of the enable and priority register configurations and the priority structure. this is detailed below along with the specifics of the interrupts unique to the 8XC552. the eight timer t2 interrupts are generated by flags cti0-ct13, cmi0-cmi2, and by the logical or of flags t2ov and t2bo. flags cti0 to ct13 are set by input signals ct0i to ct3i. flags cmi0 to cmi2 are set when a match occurs between timer t2 and the compare registers cm0, cm1, and cm2. when an 8-bit or 16-bit overflow occurs, flags t2bo and t2ov are set, respectively. these nine flags are not cleared by hardware and must be reset by software to avoid recurring interrupts. the adc interrupt is generated by the adci flag in the adc control register (adcon). this flag is set when an adc conversion result is ready to be read. adci is not cleared by hardware and must be reset by software to avoid recurring interrupts. the sio1 (i 2 c) interrupt is generated by the si flag in the sio1 control register (s1con). this flag is set when s1sta is loaded with a valid status code. the adci flag may be reset by software. it cannot be set by software. all other flags that generate interrupts may be set or cleared by software, and the effect is the same as setting or resetting the flags by hardware. thus, interrupts may be generated by software and pending interrupts can be canceled by software. interrupt enable registers: each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function registers ien0 and ien1. all interrupt sources can also be globally enabled or disabled by setting or clearing bit ea in ien0. the interrupt enable registers are described in figures 28 and 29. interrupt priority structure: each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority special function registers ip0 and ip1. ip0 and ip1 are described in figures 30 and 31. interrupt priority levels are as follows: a0oelow priority a1oehigh priority a low priority interrupt may be interrupted by a high priority interrupt. a high priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority occur simultaneously, the high priority level request is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling sequence. this second priority structure is shown in table 8. the above priority within level structure is only used when there are simultaneous requests of the same priority level. interrupt handling: the interrupt sources are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware-generated lcall is not blocked by any of the following conditions: 1. an interrupt of higher or equal priority level is already in progress. 2. the current machine cycle is not the final cycle in the execution of the instruction in progress. (no interrupt request will be serviced until the instruction in progress is completed.) 3. the instruction in progress is reti or any access to the interrupt priority or interrupt enable registers. (no interrupt will be serviced after reti or after a read or write to ip0, ip1, ie0, or ie1 until at least one other instruction has been subsequently executed.) the polling cycle is repeated with every machine cycle, and the values polled are the values present at s5p2 of the previous machine cycle. note that if an interrupt flag is active but is not being responded to because of one of the above conditions, and if the flag is inactive when the blocking condition is removed, then the blocked interrupt will not be serviced. thus, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate service routine. in some cases it also clears the flag which generated the interrupt, and in others it does not. it clears the timer 0, timer 1, and external interrupt flags. an external interrupt flag (ieo or ie1) is cleared only if it was transition-activated. all other interrupt flags are not cleared by hardware and must be cleared by the software. the lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to as shown in table 9. execution proceeds from the vector address until the reti instruction is encountered. the reti instruction clears the apriority level activeo flip-flop that was set when this interrupt was acknowledged. it then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it was interrupted.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 43 global enable interrupt priority registers polling hardware high prior- ity interrupt request external interrupt request 0 int0 a1 a2 source identification vector a1 b1 source enable interrupt enable registers interrupt sources i 2 c serial port b1 b2 c1 d1 adc c1 c2 e1 f1 timer 0 overflow d1 d2 g1 h1 timer 2 capture 0 e1 e2 i1 j1 timer 2 compare 0 f1 f2 k1 l1 external interrupt request 1 g1 g2 m1 n1 timer 2 capture 1 h1 h2 o1 i1 i2 j1 j2 k1 k2 l1 l2 m1 m2 n1 n2 o1 o2 low prior- ity interrupt request source identification vector a2 b2 c2 d2 e2 f2 g2 h2 i2 j2 k2 l2 m2 n2 o2 timer 2 compare 1 timer 1 overflow timer 2 capture 2 timer 2 compare 2 timer 2 capture 3 timer t2 overflow int1 uart serial port t r ct0i ct1i ct2i ct3i figure 27. the interrupt system
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 44 ex0 bit symbol function ien0.7 ea global enable/disable control 0 = no interrupt is enabled 1 = any individually enabled interrupt will be accepted ien0.6 ead eanble adc interrupt ien0.5 es1 enable sio1 (i 2 c) interrupt ien0.4 es0 enable sio0 (uart) interrupt ien0.3 et1 enable timer 1 interrupt ien0.2 ex1 enable external interrupt 1 ien0.1 et0 enable timer 0 interrupt ien0.0 ex0 enable external interrupt 0 su00762 et0 ex1 et1 es0 es1 ead ea 0 1 2 3 4 5 6 7 (lsb) (msb) ien0 (a8h) figure 28. interrupt enable register (ien0) ect0 bit symbol function ien1.7 et2 enable timer t2 overflow interrupt(s) ien1.6 ecm2 enable t2 comparator 2 interrupt ien1.5 ecm1 enable t2 comparator 1 interrupt ien1.4 ecm0 enable t2 comparator 0 interrupt ien1.3 ect3 enable t2 capture register 3 interrupt ien1.2 ect2 enable t2 capture register 2 interrupt ien1.1 ect1 enable t2 capture register 1 interrupt ien1.0 ect0 enable t2 capture register 0 interrupt su00755 ect1 ect2 ect3 ecm0 ecm1 ecm2 et2 0 1 2 3 4 5 6 7 (lsb) (msb) ien1 (e8h) in all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled . figure 29. interrupt enable register (ien1) px0 bit symbol function ip0.7 unused ip0.6 pad adc interrupt priority level ip0.5 ps1 sio1 (i 2 c) interrupt priority level ip0.4 ps0 sio0 (uart) interrupt priority level ip0.3 pt1 timer 1 interrupt priority level ip0.2 px1 external interrupt 1 priority level ip0.1 pt0 timer 0 interrupt priority level ip0.0 px0 external interrupt 0 priority level su00763 pt0 px1 pt1 ps0 ps1 pad 0 1 2 3 4 5 6 7 (lsb) (msb) ip0 (b8h) figure 30. interrupt priority register (ip0)
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 45 pct0 bit symbol function ip1.7 pt2 t2 overflow interrupt(s) priority level ip1.6 pcm2 t2 comparator 2 interrupt priority level ip1.5 pcm1 t2 comparator 1 interrupt priority level ip1.4 pcm0 t2 comparator 0 interrupt priority level ip1.3 pct3 t2 capture register 3 interrupt priority level ip1.2 pct2 t2 capture register 2 interrupt priority level ip1.1 pct1 t2 capture register 1 interrupt priority level ip1.0 pct0 t2 capture register 0 interrupt priority level su00764 pct1 pct2 pct3 pcm0 pcm1 pcm2 pt2 0 1 2 3 4 5 6 7 (lsb) (msb) ip1 (f8h) figure 31. interrupt priority register (ip1) table 8. interrupt priority structure source name priority within level external interrupt 0 x0 (highest) sio1 (i 2 c) s1 adc completion adc timer 0 overflow t0 t2 capture 0 ct0 t2 compare 0 cm0 external interrupt 1 x1 t2 capture 1 ct1 t2 compare 1 cm1 timer 1 overflow t1 t2 capture 2 ct2 t2 compare 2 cm2 sio0 (uart) s0 t2 capture 3 ct3 timer t2 overflow t2 (lowest) table 9. interrupt vector addresses source name vector address external interrupt 0 x0 0003h timer 0 overflow t0 000bh external interrupt 1 x1 0013h timer 1 overflow t1 001bh sio0 (uart) s0 0023h sio1 (i 2 c) s1 002bh t2 capture 0 ct0 0033h t2 capture 1 ct1 003bh t2 capture 2 ct2 0043h t2 capture 3 ct3 004bh adc completion adc 0053h t2 compare 0 cm0 005bh t2 compare 1 cm1 0063h t2 compare 2 cm2 006bh t2 overflow t2 0073h
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 46 i/o port structure the 8XC552 has six 8-bit ports. each port consists of a latch (special function registers p0 to p5), an input buffer, and an output driver (port 0 to 4 only). ports 0-3 are the same as in the 80c51, with the exception of the additional functions of port 1. the parallel i/o function of port 4 is equal to that of ports 1, 2, and 3. port 5 may be used as an input port only. figure 32 shows the bit latch and i/o buffer functional diagrams of the unique 8XC552 ports. a bit latch corresponds to one bit in a port's sfr and is represented as a d type flip-flop. a awrite to latcho signal from the cpu latches a bit from the internal bus and a aread latcho signal from the cpu places the q output of the flip-flop on the internal bus. a aread pino signal from the cpu places the actual port pin level on the internal bus. some instructions that read a port read the actual port pin levels, and other instructions read the latch (sfr) contents. port 1 operation port 1 operates the same as it does in the 8051 with the exception of port lines p1.6 and p1.7, which may be selected as the scl and sda lines of serial port sio1 (i 2 c). because the i 2 c bus may be active while the device is disconnected from v dd , these pins are provided with open drain drivers. therefore pins p1.6 and p1.7 do not have internal pull-ups. port 5 operation port 5 may be used to input up to 8 analog signals to the adc. unused adc inputs may be used to input digital inputs. these inputs have an inherent hysteresis to prevent the input logic from drawing excessive current from the power lines when driven by analog signals. channel to channel crosstalk (ct) should be taken into consideration when both analog and digital signals are simultaneously input to port 5 (see, d.c. characteristics in data sheet). port 5 is not bidirectional and may not be configured as an output port. all six ports are multifunctional, and their alternate functions are listed in table 10. a more detailed description of these features can be found in the relevant parts of this section. pulse width modulated outputs the 8XC552 contains two pulse width modulated output channels (see figure 33). these channels generate pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1. the pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. buffered pwm outputs may be used to drive dc motors. the rotation speed of the motor would be proportional to the contents of pwmn. the pwm outputs may also be configured as a dual dac. in this application, the pwm outputs must be integrated using conventional operational amplifier circuitry. if the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the pwm outputs before they are integrated. the repetition frequency f pwm , at the pwmn outputs is give by: f pwm f osc 2 (1 pwmp) 255 this gives a repetition frequency range of 123hz to 31.4khz (f osc = 16mhz). at fosc = 24mhz, the frequency range is 184hz to 47.1hz. by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. both pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. prescaler frequency control register pwmp pwmp (feh) 76 5 432 10 msb lsb pwmp.0-7 prescaler division factor = pwmp + 1. reading pwmp gives the current reload value. the actual count of the prescaler cannot be read. pwm0 (fch) pwm1 (fdh) 76 5 43 2 10 msb lsb pwm0/1.0-7} low/high ratio of pwmn (pwmn) 255 (pwmn) analog-to-digital converter the analog input circuitry consists of an 8-input analog multiplexer and a 10-bit, straight binary, successive approximation adc. the analog reference voltage and analog power supplies are connected via separate input pins. the conversion takes 50 machine cycles, i.e., 37.5 m s at an oscillator frequency of 16mhz, 25 m s at an oscillator frequency of 24mhz. input voltage swing is from 0v to +5v. because the internal dac employs a ratiometric potentiometer, there are no discontinuities in the converter characteristic. figure 34 shows a functional diagram of the analog input circuitry.
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 47 p1.x latch dq cl q read latch int . bus write to latch read pin alternate input function v dd p1.x pin * internal pull-up a. p5.x pin int . bus read pin d. ) p1.x latch dq cl q read latch int . bus write to latch read pin alternate input function v dd p3.x pin * internal pull-up b. ) alternate output function p4.x latch dq cl q read latch int . bus write to latch read pin v dd p4.x pin * internal pull-up c. ) note: pull-up not present on p1.6 and p1.7. *two period active pull-up as in the 80c51. set from alternate function clear from alternate function to adc figure 32. port bit latches and i/o buffers
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 48 table 10. input/output ports port pin alternate function p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 multiplexed lower order address/data bus used during external memory accesses p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ct0i ct1i ct2i ct3i t2 rt2 scl sda capture timiner input signals for timer t2 t2 event input t2 timer reset signal. rising edge triggered serial port clock line i 2 c bus serial port data line i 2 c bus p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 a8 a9 a10 a11 a12 a13 a14 a15 high order address byte used during external memory accesses p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 rxd txd int0 int1 t0 t1 wr rd serial input port (uart) serial output port (uart) external interrupt 0 external interrupt 1 timer 0 external input timer 1 external input external data memory write strobe external data memory read strobe p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 cmsr0 cmsr1 cmsr2 cmsr3 cmsr4 cmsr5 cmt0 cmt1 timer t2: compare and set/reset outputs on a match with timer t2 timer t2: compare and toggle outputs on a match with timer t2 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 eight analogue adc inputs
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 49 internal bus pwm0 f osc 8-bit comparator 8-bit counter 8-bit comparator pwm1 prescaler 1/2 output buffer pwmp output buffer pwm0 pwm1 figure 33. functional diagram of pulse width modulated outputs internal bus 10-bit a/d converter analog input multiplexer 01234567 01234567 + stadc analog ref. analog supply analog ground adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 adcon adch figure 34. functional diagram of analog input circuitry
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 50 analog-to-digital conversion: figure 35 shows the elements of a successive approximation (sa) adc. the adc contains a dac which converts the contents of a successive approximation register to a voltage (vdac) which is compared to the analog input voltage (vin). the output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. a conversion is initiated by setting adcs in the adcon register. adcs can be set by software only or by either hardware or software. the software only start mode is selected when control bit adcon.5 (adex) = 0. a conversion is then started by setting control bit adcon.3 (adcs). the hardware or software start mode is selected when adcon.5 = 1, and a conversion may be started by setting adcon.3 as above or by applying a rising edge to external pin stadc. when a conversion is started by applying a rising edge, a low level must be applied to stadc for at least one machine cycle followed by a high level for at least one machine cycle. the low-to-high transition of stadc is recognized at the end of a machine cycle, and the conversion commences at the beginning of the next cycle. when a conversion is initiated by software, the conversion starts at the beginning of the machine cycle which follows the instruction that sets adcs. adcs is actually implemented with two flip-flops: a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. the next two machine cycles are used to initiate the converter. at the end of the first cycle, the adcs status flag is set and a value of a1o will be returned if the adcs flag is read while the conversion is in progress. sampling of the analog input commences at the end of the second cycle. during the next eight machine cycles, the voltage at the previously selected pin of port 5 is sampled, and this input voltage should be stable in order to obtain a useful sample. in any event, the input voltage slew rate must be less than 10v/ms in order to prevent an undefined result. the successive approximation control logic first sets the most significant bit and clears all other bits in the successive approximation register (10 0000 0000b). the output of the dac (50% full scale) is compared to the input voltage vin. if the input voltage is greater than vdac, then the bit remains set; otherwise it is cleared. the successive approximation control logic now sets the next most significant bit (11 0000 0000b or 01 0000 0000b, depending on the previous result), and vdac is compared to vin again. if the input voltage is greater than vdac, then the bit being tested remains set; otherwise the bit being tested is cleared. this process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approximation register. figure 36 shows a conversion flow chart. the bit pointer identifies the bit under test. the conversion takes four machine cycles per bit. the end of the 10-bit conversion is flagged by control bit adcon.4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adcon.7 (adc.1) and adcon.6 (adc.0). the user may ignore the two least significant bits in adcon and use the adc as an 8-bit converter (8 upper bits in adch). in any event, the total actual conversion time is 50 machine cycles for the 8XC552 or 24 machine cycles for the 8xc562. adci will be set and the adcs status flag will be reset 50 (or 24) cycles after the command flip-flop (adcs) is set. control bits adcon.0, adcon.1, and adcon.2 are used to control an analog multiplexer which selects one of eight analog channels (see figure 37). an adc conversion in progress is unaffected by an external or software adc start. the result of a completed conversion remains unaffected provided adci = logic 1; a new adc conversion already in progress is aborted when the idle or power-down mode is entered. the result of a completed conversion (adci = logic 1) remains unaffected when entering the idle mode. successive approximation control logic successive approximation register dac + start stop v in v dac 0 1 234 56 t/tau v dac full scale 1 v in 1/2 3/4 7/8 15/16 29/32 59/64 figure 35. successive approximation adc
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 51 eoc soc reset sar start of conversion end of conversion [bit pointer] = msb [bit] n = 1 conversion time test complete [bit] n = 0 [bit pointer] + 1 test bit pointer 10 end end figure 36. a/d conversion flowchart (msb) (lsb) aadr2 aadr1 aadr0 765 4 3210 adcon (c5h) adcon.7 adc.1 bit 1 of adc result bit 0 of adc result enable external start of conversion by stadc 0 = conversion can be started by software only (by setting adcs) 1 = conversion can be started by software or externally (by a rising edge on stadc) bit symbol function adex adci adcs adc.1 adc.0 adcon.6 adc.0 adcon.5 adex adc interrupt flag: this flag is set when an a/d conversion result is ready to be read. an interrupt is invoked if it is enable d. the flag may be cleared by the interrupt service routine. while this flag is set, the adc cannot start a new conversion. adci cannot be set by software. adcon.4 adci adc start and status: setting this bit starts an a/d conversion. it may be set by software or by the external signal stadc. the adc logic ensures that this signal is high while the adc is busy. on completion of the conversion, adcs is reset immediately after the in terrupt flag has been set. adcs cannot be reset by software. a new conversion may not be started while either adcs or adci is high. adcon.3 adcs adci adcs adc status 0 0 adc not busy; a conversion can be started 0 1 adc busy; start of a new conversion is blocked 1 0 conversion completed; start of a new conversion requires adci=0 1 1 conversion completed; start of a new conversion requires adci=0 adcon.2 aadr2 adcon.1 aadr1 adcon.0 aadr0 analogue input select: this binary coded address selects one of the eight analogue port bits of p5 to be input to the converter. it can only be changed when adci and adcs are both low. aadr2 aadr1 selected analog channel 0 0 adc0 (p5.0) 0 0 adc1 (p5.1) aadr0 0 1 0 1 adc2 (p5.2) 0 0 1 adc3 (p5.3) 1 1 0 adc4 (p5.4) 0 1 0 adc5 (p5.5) 1 1 1 adc6 (p5.6) 0 1 1 adc7 (p5.7) 1 if adci is cleared by software while adcs is set at the same time, a new a/d conversion with the same channel number may be sta rted. but it is recommended to reset adci before adcs is set. figure 37. adc control register (adcon)
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 52 adc resolution and analog supply: figure 38 shows how the adc is realized. the adc has its own supply pins (av dd and av ss ) and two pins (vref+ and vref) connected to each end of the dac's resistance-ladder. the ladder has 1023 equally spaced taps, separated by a resistance of aro. the first tap is located 0.5 x r above vref, and the last tap is located 1.5 x r below vref+. this gives a total ladder resistance of 1024 x r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error as shown in figure 40. for input voltages between vref and (vref) + 1/2 lsb, the 10-bit result of an a/d conversion will be 00 0000 0000b = 000h. for input voltages between (vref+) 3/2 lsb and vref+, the result of a conversion will be 11 1111 1111b = 3ffh. avref+ and avref may be between av dd + 0.2v and av ss 0.2v. avref+ should be positive with respect to avref, and the input voltage (vin) should be between avref+ and avref. if the analog input voltage range is from 2v to 4v, then 10-bit resolution can be obtained over this range if avref+ = 4v and avref = 2v. the result can always be calculated from the following formula: result 1024 v in av ref av ref av ref power reduction modes the 8XC552 has two reduced power modes of operation: the idle mode and the power-down mode. these modes are entered by setting bits in the pcon special function register. when the 8XC552 enters the idle mode, the following functions are disabled: cpu (halted) timer t2 (halted and reset) pwm0, pwm1 (reset; outputs are high) adc (conversion aborted if in progress). in idle mode, the following functions remain active: timer 0 timer 1 timer t3 sio0 sio1 external interrupts when the 8XC552 enters the power-down mode, the oscillator is stopped. the power-down mode is entered by setting the pd bit in the pcon register. the pd bit can only be set if the ew input is tied high. successive approximation control logic successive approximation register + decoder msb comparator lsb start ready av ref+ av ref r/2 r r r r r r/2 total resistance = 1023r + 2 x r/ = 1024r v ref v in 1023 1022 1021 3 2 1 0 value 0000 0000 00 is output for voltages v ref to (v ref + 1/2 lsb) value 1111 1111 11 is output for voltages (v ref+ 3/2 lsb) to v ref+ figure 38. adc realization
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 53 r s v analog input c s c c to comparator + i n i n+1 sm n+1 sm n rm n+1 rm n multiplexer rm = 0.5 - 3 kohms cs + cc = 15pf maximum rs = recommended < 9.6 kohms for 1 lsb @ 12mhz note: because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. when a conversio n is initiated, switch sm closes for 8tcy (8 m s @ 12mhz crystal frequency) during which time capacitance cs + cc is charged. it should be noted that the sampling causes the analog input to present a varying load to an analog source. figure 39. a/d input: equivalent circuit 0 q 2q 3q 4q 5q v in code out 100 000 001 010 011 101 quantization error q = lsb = 5 mv v in v digital + q/2 q/2 v in symmetrical quantization error figure 40. effective conversion characteristic
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 54 power-down mode: the instruction that sets pcon.1 will be the last instruction executed in the normal operating mode before the power-down mode is entered. in the power-down mode, the on-chip oscillator is stopped. this freezes all functions; only the on-chip ram and special function registers are held. the port pins output the contents of their respective special function registers. a hardware reset is the only way to terminate the power-down mode. reset re-defines all the special function registers, but does not change the on-chip ram. in the power-down mode, v dd and av dd can be reduced to minimize power consumption. v dd and av dd must not be reduced before the power-down mode is entered and must be restored to the normal operating voltage before the power-down mode is terminated. the reset that terminates the power-down mode also freezes the oscillator. the reset should not be activated before v dd and av dd are restored to their normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10ms). the status of the external pins during power-down is shown in table 11. if the power-down mode is entered while the 8XC552 is executing out of external program memory, the port data that is held in the p2 special function register is restored to port 2. if a port latch contains a a1o, the port pin is held high during the power-down mode by the strong pull-up transistor. power control register pcon: the idle and power-down modes are entered by writing to bits in pcon. pcon is not bit addressable. see figure 41. memory organization the memory organization of the 8XC552 is the same as in the 80c51, with the exception that the 8XC552 has 8k rom, 256 bytes ram, and additional sfrs. addressing modes are the same in the 8XC552 and the 80c51. details of the differences are given in the following paragraphs. in the 8XC552, the lower 8k of the 64k program memory address space is filled by internal rom. by tying the ea pin high, the processor fetches instructions from internal program rom. bus expansion for accessing program memory from 8k upwards is automatic since external instruction fetches occur automatically when the program counter exceeds 8191. if the ea pin is tied low, all program memory fetches are from external memory. the execution speed of the 8XC552 is the same regardless of whether fetches are from external or internal program memory. if all storage is on-chip, then byte location 8191 should be left vacant to prevent an undesired pre-fetch from external program memory address 8192. certain locations in program memory are reserved for specific programs. locations 0000h to 0002h are reserved for the initialization program. following reset, the cpu always begins execution at locations 0000h. locations 0003h to 0075h are reserved for the fifteen interrupt request service routines. functionally, the internal data memory is the most flexible of the address spaces. the internal data memory space is subdivided into a 256-byte internal data ram address space and a 128-byte special function register (sfr) address space, as shown in figure 42. the internal data ram address space is 0 to 255. four 8-bit register banks occupy locations 0 to 31. 128 bit locations of the internal data ram are accessible through direct addressing. these bits reside in 16 bytes of internal data ram at locations 20h to 2fh. the stack can be located anywhere in the internal data ram address space by loading the 8-bit stack pointer. the stack depth may be 256 bytes maximum. the sfr address space is 128 to 255. all registers except the program counter and the four 8-bit register banks reside in this address space. memory mapping the sfrs allows them to be accessed as easily as internal ram, and as such, they can be operated on by most instructions. the 56 sfrs are listed in figure 43, and their mapping in the sfr address space is shown in figures 44 and 45. ram bit addresses are the same as in the 80c51 and are summarized in figure 46. the special function bit addresses are summarized in figure 47. table 11. external pin status during idle and power-down modes mode memory ale psen port 0 port 1 port 2 port 3 port 4 pwm0 /pwm1 idle (1) internal 1 1 port data port data port data port data port data high idle (1) external 1 1 floating port data address port data port data high power-down internal 0 0 port data port data port data port data port data high power-down external 0 0 floating port data port data port data port data high
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 55 smod wle gf1 gf0 pd idl 76543210 pcon (87h) pcon.7 smod double baud rate bit. when set to logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2, or 3. pcon.6 (reserved) pcon.5 (reserved) pcon.4 wle watchdog load enable. this flag must be set by software prior to loading timer t3 (watch- dog timer). it is cleared when timer t3 is loaded. pcon.3 gf1 general-purpose flag bit pcon.2 gf0 general-purpose flag bit pcon.1 pd power-down bit. setting this bit activates the power-down mode. it can only be set if input ew is high. pcon.0 idl idle mode bit. setting this bit activates the idle mode. bit symbol function if logic 1s are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is (0xx00000). figure 41. power control register (pcon) 255 255 upper 128 bytes internal ram special function registers indirect addressing only direct addressing only 128 direct or indirect addressing overlapped space 127 48 127 120 32 70 24 r0 bank 3 r7 16 r0 bank 2 r7 8 r0 bank 1 r7 0 r0 bank 1 r7 addressable bits in ram (128 bits) registers internal data ram figure 42. internal data memory address space arithmetic registers: accumulator,* b register,* program status word* pointers: stack pointer, data pointer (high and low) parallel i/o ports: port 5,* port 4,*port 3,* port 2,* port 1,* port 0* interrupt system: interrupt priority 0,* interrupt priority 1,* interrupt enable 0,* interrupt enable 1* pulse width modulated o/ps: pulse width modulation prescaler pulse width modulation register 0, pulse width modulation register 1 serial i/o ports: serial 0 control,* serial 0 data buffer, serial 1 control,* serial 1 data, serial 1 status, serial 1 address, pcon timers: timer mode, timer control,* timer low 0, timer high 0, timer low 1, timer high 1, timer t2 control, timer low 2, timer high 2, timer t3 capture and compare logic: capture control, timer t2 interrupt flag register, capture low 0, capture high 0, capture low 1, capture high 1, capture low 2, capture high 2, capture low 3, capture high 3, compare low 0, compare high 0, compare low 1, compare high 1, compare low 2, compare high 2 set enable, reset enable adc adc control, adc high byte *note: bit and byte addressable figure 43. special function registers
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 56 t3 f0 f1 f3 f2 f4 f5 f7 f6 f8 f9 fb fa fc fd ff fe e0 e1 e3 e2 e4 e5 e7 e6 e8 e9 eb ea ec ed ef ee d0 d1 d3 d2 d4 d5 d7 d6 d8 d9 db da dc dd df de c8 c9 cb ca cc cd cf ce c0 c1 c3 c2 c4 c5 c7 c6 pwmp pwm1 pwm0 ip1 b rte ste # tmh2 # tml2 ctcon tm2con ien1 acc s1adr s1dat # s1sta s1con psw # cth3 # cth2 # cth1 cmh2 cmh1 cmh0 # cth0 tm2ir # adch adcon # p5 p4 ffh feh fdh fch f8h foh efh eeh edh ech ebh eah e8h e0h dbh dah d9h d8h d0h cfh ceh cdh cbh cah c9h cch c8h c6h c5h c4h c0h register mnemonic bit address direct byte ad- dress (hex) sfrs containing directly addressable bits b0 b1 b3 b2 b4 b5 b7 b6 b8 b9 bb ba bc bd bf be a0 a1 a3 a2 a4 a5 a7 a6 a8 a9 ab aa ac ad af ae 90 91 93 92 94 95 97 96 98 99 9b 9a 9c 9d 9f 9e 88 89 8b 8a 8c 8d 8f 8e 80 81 83 82 84 85 87 86 ip0 p3 # ctl3 # ctl2 # ctl1 # ctl0 cml2 cml1 ien0 p2 p1 cml0 th1 s0con tl1 tl0 tmod th0 tcon pcon dph dpl p0 b8h b0h afh aeh adh ach abh aah a0h 98h 90h 8dh 8ch 8ah 88h 87h 83h 82h 81h 80h 89h 99h register mnemonic bit address direct byte ad- dress (hex) sfrs containing directly addressable bits s0buf sp a9h a8h 8bh figure 44. mapping of special function registers
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 57 255 direct addressing (bits) 128 special function registers 127 48 127 120 32 70 24 r0 bank 3 r7 16 r0 bank 2 r7 8 r0 bank 1 r7 0 r0 bank 1 r7 direct addressing (bits) register addressing direct addressing 248 240 232 224 216 208 200 192 184 176 168 160 152 144 136 f8h f0h e8h e0h d8h d0h c8h c0h b8h b0h a8h a0h 255 248 135 128 98h 90h 88h 80h stack-pointer register-indirect and register-indirect addressing figure 45. bit and byte addressing overview of internal data memory
philips semiconductors 80c51 family derivatives 8XC552/562 overview 1996 aug 06 58 7fh 68 69 6b 6a 6c 6d 6f 6e 78 79 7b 7a 7c 7d 7f 7e 2fh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 23h 21h 20h 1fh 18h 17h 0fh 10h 08h 25h 07h 22h 24h 127 47 45 44 43 42 41 40 39 37 35 33 32 31 24 23 36 15 16 8 7 38 0 70 71 73 72 74 75 77 76 2eh 46 50 51 53 52 54 55 57 56 60 61 63 62 64 65 67 66 58 59 5b 5a 5c 5d 5f 5e 40 41 43 42 44 45 47 46 48 49 4b 4a 4c 4d 4f 4e 28 29 2b 2a 2c 2d 2f 2e 38 39 3b 3a 3c 3d 3f 3e 30 31 33 32 34 35 37 36 18 19 1b 1a 1c 1d 1f 1e 20 21 23 22 24 25 27 26 00 01 03 02 04 05 07 06 10 11 13 12 14 15 17 16 08 09 0b 0a 0c 0d 0f 0e 00h 34 bank 3 bank 2 bank 1 bank 0 (msb) (lsb) figure 46. ram bit addresses pct0 pct1 pct3 pct2 pcm0 pcm1 pcm2 f8h f0h e8h e0h d8h d0h b8h c0h a8h b0h a0h 98h 90h 80h ip1 b ien1 acc psw p4 ip0 p3 ien0 p2 s0con p0 p1 tcon tm2ir register mnemonic bit address direct byte ad- dress (hex) c8h 88h s1con f8 f9 fb fa fc fd ff fe f0 f1 f3 f2 f4 f5 f7 f6 ect0 ect1 ect3 ect2 ecm0 ecm1 et2 ecm2 e8 e9 eb ea ec ed ef ee e0 e1 e3 e2 e4 e5 e7 e6 cr0 cr1 si aa sto sta cr2 ens1 d8 d9 db da dc dd df de p f1 rs0 ov rs1 f0 cy ac d0 d1 d3 d2 d4 d5 d7 d6 cti0 cti1 cti3 cti2 cmi0 cmi1 t2ov cmi2 c8 c9 cb ca cc cd cf ce c0 c1 c3 c2 c4 c5 c7 c6 px0 pt0 pt1 px1 ps0 ps1 pad b8 b9 bb ba bc bd bf be b0 b1 b3 b2 b4 b5 b7 b6 ex0 et0 et1 ex1 es0 es1 ea ead a8 a9 ab aa ac ad af ae a0 a1 a3 a2 a4 a5 a7 a6 ri ti tb8 rb8 ren sm2 sm0 sm1 98 99 9b 9a 9c 9d 9f 9e 90 91 93 92 94 95 97 96 it0 ie0 ie1 it1 tr0 tf0 tf1 tr1 88 89 8b 8a 8c 8d 8f 8e 80 81 83 82 84 85 87 86 pt2 figure 47. special function register bit address
philips semiconductors 8XC552/562 overview 80c51 family derivatives 1996 aug 06 59 notes
philips semiconductors 8XC552/562 overview 80c51 family derivatives 1996 aug 06 60 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 08-98 document order number: 9397 750 04292

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